This application relies for priority upon Korean Patent Application No. 2000-2039, filed on Jan. 17, 2000, the contents of which are herein incorporated by reference in their entirety.
This invention relates to semiconductor device and methods of fabricating the same and, more particularly, to NAND-type flash memory devices and methods of fabricating the same.
Non-volatile memory devices such as flash memory devices do not lose data stored in their memory cells when the electric power supplied to the device is interrupted. Thus, the flash memory device is widely used in memory cards or the like. Flash memory devices are generally of two types: the NAND-type flash memory device and the NOR-type flash memory device.
A cell array region of the NAND-type flash memory device comprises a plurality of strings. The string typically includes a string selection transistor, a plurality of cell transistors and a ground selection transistor, which are serially connected. The drain region of the string selection transistor is connected to a bit line, and the source region of the ground selection transistor is connected to a common source line.
A cell array region of the NOR-type flash memory device contains a plurality of cell transistors, bit lines and common source lines. Here, only one cell transistor is electrically interposed between the bit line and the common source line.
Accordingly, the NAND-type flash memory device has higher integration density and smaller cell current as compared to the NOR-type flash memory device. The cell current corresponds to current flowing through the bit line and the common source line during a read mode. Thus, it is required to increase the cell current of the NAND-type flash memory device more so than it is in the NOR-type flash memory device. This is because the cell current directly affects access time of the flash memory device. As a result, it is required to decrease electrical resistance of the bit line and/or the common source line in order to improve the access time of NAND-type flash memory device.
FIG. 1 is a top plan view showing a portion of cell array region of a conventional NAND-type flash memory device. Also, FIG. 2A is a cross-sectional view along the line Ixe2x80x94I of FIG. 1, and FIG. 2B is a cross-sectional view along the line IIxe2x80x94II of FIG. 1.
Referring to FIGS. 1, 2A and 2B, an isolation layer 1a defining a plurality of active regions 1 is formed at a predetermined region of a semiconductor substrate 10. The active regions 1 are defined in parallel to each other. A string selection line pattern 2s, first to nth word line patterns WP1 to WPn, and a ground selection line pattern 2g are formed across the isolation layer 1a and the active regions 1. Impurity regions 7, 7d and 7s are formed at the active regions 1 among the string selection line pattern 2s, the first to nth word line patterns WP1 to WPn, and the ground selection line pattern 2g. Here, the impurity region 7d formed at one side of the string selection line pattern 2s acts as a drain region of the string selection transistor. Also, the impurity region 7s formed at one side of the ground selection line pattern 2g acts as a source region of the ground selection transistor.
Accordingly, the string selection transistor is formed at a portion at which the string selection line pattern 2s and the active region 1 intersect each other. Similarly, the ground selection transistor is formed at a portion at which the ground selection line pattern 2g and the active region 1 intersect each other. Also, the cell transistors are formed at portions at which the word line patterns WP1 to WPn and the active region 1 intersect each other. As a result, a string is formed at each active region 1. Here, the string includes the string selection transistor, the cell transistors and the ground selection transistor that are serially connected.
A first interlayer insulating layer 4 is formed on the entire surface of the substrate including the strings. The first interlayer insulating layer 4 is patterned to form common source line contact holes 3 exposing the respective source regions 7s. A conductive layer filling the common source line contact holes 3, e.g., a doped polysilicon layer, is then formed on the first interlayer insulating layer 4. The conductive layer is patterned to form a common source line 5 covering the common source line contact holes 3. The common source line 5 is electrically connected to the source regions 7s through the common source line contact holes 3.
The common source line 5 and the first interlayer insulating layer 4 are covered with a second interlayer insulating layer 6. The second interlayer insulating layer 6 and the first insulating layer 4 are successively patterned to form bit line contact holes 8 exposing the respective drain regions 7d. Bit line contact plugs 8a are formed in the respective bit line contact holes 8. A metal layer is formed on the entire surface of the resultant structure where the bit line contact plugs 8a are formed. The metal layer is then patterned to form a plurality of bit lines 9 covering the respective bit line contact plugs 8a. The plurality of bit lines 9 cross over the first to nth word line patterns WP1 to WPn.
As described above, according to the conventional technology, the common source line is interposed between the first and second interlayer insulating layers. Thus, the thickness of the common source line should be increased in. order to reduce the resistance of the common source line. However, in the event that the thickness of the common source line is increased, the thickness of the second interlayer insulating layer should be also increased in order to enhance the isolation characteristic between the bit lines and the common source line. At this time, the aspect ratio of the bit line contact holes penetrating the first and second interlayer insulating layers is increased. As a result, it is required to minimize the resistance of the common source line as well as the aspect ratio of the bit line contact holes.
It is therefore a feature of the present invention to provide a NAND-type flash memory device having low resistance in a common source line as well as low aspect ratio of the bit line contact holes. It is another feature of the present invention to provide methods of fabricating a NAND-type flash memory device, which can minimize the aspect ratio of the bit line contact holes and the resistance of the common source line.
These and other features of the present invention may be provided by a NAND-type flash memory device according to the invention. The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. A string selection line pattern and a ground selection line pattern cross over active regions between the plurality of isolation layers. The string selection line pattern and the ground selection line pattern run parallel with each other. A plurality of word line patterns is disposed between the string selection line pattern and the ground selection line pattern. Source regions are formed at the active regions adjacent to the ground selection line patterns. The source regions are located opposite the string selection line pattern. Drain regions are formed at the active regions adjacent to the string selection line patterns, the drain regions being located opposite the ground selection line pattern. A common source line is disposed on the source regions and the isolation layers between the source regions, the common source line running parallel with the ground selection line pattern and being electrically connected to the source regions.
A plurality of bit lines are disposed across the plurality of word line patterns and the common source line. The respective bit lines are electrically connected to the respective drain regions. A drain contact plug may be interposed between the bit line and the drain region. Also, first and second interlayer insulating layers, which are sequentially stacked, are interposed between the bit lines and the word line patterns. Here, the second interlayer insulating layer is interposed between the bit lines and the common source line.
In one embodiment, the common source line is formed of a doped polysilicon layer and/or a refractory metal polycide layer in order to reduce the resistance of the common source line. Also, the top surface of the common source line may be even with or lower than that of the first interlayer insulating layer.
In accordance with another feature of the present invention, there is provided a method of fabricating a NAND-type flash memory device. This method includes forming a first interlayer insulating layer on an entire surface of a substrate having a plurality of strings which are parallel to each other, patterning the first interlayer insulating layer to form a slit-type common source line contact hole exposing source regions of the respective strings and isolation layers between the source regions, and forming a common source line in the slit-type common source line contact hole. Here, drain regions of the respective strings may be exposed by drain contact holes during formation of the common source line contact hole.
The method of forming the plurality of strings includes forming an isolation layer defining a plurality of active regions-which run parallel with each other at a predetermined region of a semiconductor substrate, forming a tunnel oxide layer on the active regions, and forming a string selection line pattern, a plurality of word line patterns, and a ground selection line pattern crossing over the active regions covered by the tunnel oxide layer and isolation layer between the active regions. In addition, the method of forming the plurality of strings includes ion implanting impurities into the active regions among the string selection line pattern, the plurality of word line patterns, and the ground selection line pattern, thereby forming drain regions at the active regions adjacent to the string selection line pattern and opposite the ground selection line pattern and concurrently forming source regions at the active regions adjacent to the ground selection line pattern and opposite the string selection line pattern.
Alternatively, the plurality of strings may be formed using a self-aligned shallow trench isolation technique. Specifically, this method includes the steps of sequentially forming a tunnel oxide layer and a first conductive layer on a semiconductor substrate. The first conductive layer and the tunnel oxide layer are successively patterned to form a first conductive layer pattern exposing a predetermined portion of the semiconductor substrate. The exposed substrate is etched to form a trench region defining a plurality of active regions, which run parallel with each other. The trench region is filled with an isolation layer. The first conductive layer pattern and the isolation layer are covered with a second conductive layer. The second conductive layer is patterned to form a second conductive layer pattern exposing the isolation layer. An inter-gate dielectric layer and a third conductive layer are sequentially formed on the entire surface of the substrate including the second conductive layer pattern. The third conductive layer, the intergate dielectric layer, the second conductive layer pattern and the first conductive layer pattern are successively patterned to form a string selection line pattern, a plurality of word line patterns and a ground selection line pattern crossing over the active regions covered with the tunnel oxide layer and the isolation layer between the active regions. Impurities are ion-implanted into the active regions among the string selection line pattern, the plurality of word line patterns and the ground selection line pattern, thereby forming drain regions at the active regions adjacent to the string selection line pattern and opposite the ground selection line pattern and concurrently forming source regions at the active regions adjacent to the ground selection line pattern and opposite the string selection line pattern.
In one embodiment, an etch stop layer having an etching selectivity with respect to the first interlayer insulating layer is formed prior to formation of the first interlayer insulating layer. At this time, the method of forming the slit-type common source line contact hole and the drain contact holes includes the steps of patterning the first interlayer insulating layer to selectively expose the etch stop layer on the source regions and the isolation layer between the active regions and the etch stop layer on the drain regions. The exposed etch stop layer is etched, thereby exposing the source regions and the isolation layer between the active regions and concurrently exposing the drain regions. Here, the drain contact holes exposing the respective drain regions may not be formed.
In one embodiment, the common source line is formed by depositing a conductive layer, e.g., a doped polysilicon layer, filling the common source line contact hole, on the entire surface of the substrate including the common source line contact hole and planarizing the conductive layer until the first interlayer insulating layer is exposed. Thus, the top surface of the common source line is even with or lower than that of the first interlayer insulating layer. In addition, a refractory metal silicide layer may be formed on the conductive layer pattern in order to reduce the resistance of the common source line. At this time, in the event that the drain contact holes are formed, a plurality of drain contact plugs are formed in the respective drain contact holes.
Moreover, the method according to the present invention may further includes the steps of forming a second interlayer insulating layer on the entire surface of the substrate having the common source line. The second interlayer insulating layer and the first interlayer insulating layer are successively patterned to form a plurality of bit line contact holes exposing the respective drain regions. A plurality of bit lines covering the respective bit line contact holes are then formed. A plurality of bit line contact plugs may be formed in the respective bit line contact holes prior to formation of the bit lines. In the meantime, in the event that the plurality of drain contact plugs are formed in the respective drain contact holes, the plurality of bit line contact holes expose the respective drain contact plugs. At this time, the bit line contact plug may be interposed between the drain contact plug and the bit line.